Semiconductor devices are commonly found in modern electronic products. Semiconductor devices vary in the number and density of electrical components. Discrete semiconductor devices generally contain one type of electrical component, e.g., light emitting diode (LED), small signal transistor, resistor, capacitor, inductor, and power metal oxide semiconductor field effect transistor (MOSFET). Integrated semiconductor devices typically contain hundreds to millions of electrical components. Examples of integrated semiconductor devices include microcontrollers, microprocessors, charged-coupled devices (CCDs), solar cells, and digital micro-mirror devices (DMDs).
Semiconductor devices perform a wide range of functions such as signal processing, high-speed calculations, transmitting and receiving electromagnetic signals, controlling electronic devices, transforming sunlight to electricity, and creating visual projections for television displays. Semiconductor devices are found in the fields of entertainment, communications, power conversion, networks, computers, and consumer products. Semiconductor devices are also found in military applications, aviation, automotive, industrial controllers, and office equipment.
Semiconductor devices exploit the electrical properties of semiconductor materials. The atomic structure of semiconductor material allows its electrical conductivity to be manipulated by the application of an electric field or base current or through the process of doping. Doping introduces impurities into the semiconductor material to manipulate and control the conductivity of the semiconductor device.
A semiconductor device contains active and passive electrical structures. Active structures, including bipolar and field effect transistors, control the flow of electrical current. By varying levels of doping and application of an electric field or base current, the transistor either promotes or restricts the flow of electrical current. Passive structures, including resistors, capacitors, and inductors, create a relationship between voltage and current necessary to perform a variety of electrical functions. The passive and active structures are electrically connected to form circuits, which enable the semiconductor device to perform high-speed calculations and other useful functions.
Semiconductor devices are generally manufactured using two complex manufacturing processes, i.e., front-end manufacturing, and back-end manufacturing, each involving potentially hundreds of steps. Front-end manufacturing involves the formation of a plurality of die on the surface of a semiconductor wafer. Each semiconductor die is typically identical and contains circuits formed by electrically connecting active and passive components. Back-end manufacturing involves singulating individual semiconductor die from the finished wafer and packaging the die to provide structural support and environmental isolation. The term “semiconductor die” as used herein refers to both the singular and plural form of the words, and accordingly, can refer to both a single semiconductor device and multiple semiconductor devices.
One goal of semiconductor manufacturing is to produce smaller semiconductor devices. Smaller devices typically consume less power, have higher performance, and can be produced more efficiently. In addition, smaller semiconductor devices have a smaller footprint, which is desirable for smaller end products. A smaller semiconductor die size can be achieved by improvements in the front-end process resulting in semiconductor die with smaller, higher density active and passive components. Back-end processes may result in semiconductor device packages with a smaller footprint by improvements in electrical interconnection and packaging materials.
The manufacturing of smaller semiconductor devices relies on implementing improvements to horizontal and vertical electrical interconnection between multiple semiconductor devices on multiple levels (3-D device integration). Horizontal electrical interconnections include redistribution layers (RDLs) formed as part of fan-out wafer level chip scale packages (fo-WLCSP) or embedded wafer-level ball grid arrays (eWLB), which provide electrical connection between a semiconductor die and points external the package. Vertical interconnection can be accomplished with conductive through silicon vias (TSV) or through hole vias (THV). However, the use of TSVs and THVs typically involves considerable time and equipment, which reduces the unit-per-hour (UPH) production and increases cost. Furthermore, via formation can include formation of voids that reduce device reliability, and can present problems with semiconductor die placement accuracy and warpage control. One approach to addressing the issues of horizontal and vertical interconnection for 3-D device integration, as known in the prior art, is shown in FIGS. 1a and 1b. 
FIG. 1a shows eWLB-molded laser package (MLP) package 10 that uses an interconnect structure 12 including RDLs to provide fan-out horizontal electrical connection for semiconductor die 14. eWLB-MLP package 10 also includes openings 18 formed in encapsulant 20 by laser drilling. Vertical interconnects or conductive bumps 22 are disposed within openings 18 to provide vertical interconnection between interconnect structure 12 and a surface of eWLB-MLP package 10 opposite the interconnect structure without use of TSV or THV. Accordingly, eWLB-MLP package 10 provides horizontal and vertical electrical interconnection with an interconnect I/O array of vertical interconnects 22 formed outside a footprint of semiconductor die 14 for subsequent mounting of additional semiconductor devices or packages to form a 3-D eWLB-MLP package.
FIG. 1b shows a ball grid array (BGA) package or bumped semiconductor device 24 is disposed over eWLB-MLP package 10 from FIG. 1a with bumps 26 disposed over and oriented towards bumps 22. In FIG. 1c, BGA package 24 is mounted with surface mount technology (SMT) to eWLB-MLP package 10 to form a 3-D eWLB-MLP package 28. After mounting BGA package 24 to eWLB-MLP package 10, 3-D eWLB-MLP package 28 is heated to reflow bumps 26 from BGA package 24 and vertical interconnects 22 to form bumps or interconnect structures 30. Thus, 3-D eWLB-MLP package 28 is formed and provides horizontal and vertical interconnection as a 3-D integrated semiconductor device. However, the formation of 3-D eWLB-MLP package 28 requires a complicated process flow that results in a high process cost. The process flow for 3-D eWLB-MLP package 28 is complicated by the formation of openings 18 with laser drilling and the use of two bumping processes. A first bumping process is used to form bumps 26 as part of BGA package 24, and a second bumping process is used to form bumps 22 in openings 18 as shown in FIG. 1a, which are subsequently joined to form bumps 30. The formation of 3-D eWLB-MLP package 28 also provides a challenge for handling the package during backside laser drilling and the formation of openings 18 and bumps 30. The mounting of BGA 24 to eWLB-MLP package 10 using SMT introduces additional challenges, such as handling issues and potential wafer damage, that reduce device reliability and package yield. Finally, 3-D eWLB-MLP package 28 offers limited flexibility in controlling an overall height of the package.